GRIDE – the research group on Electronic Devices of the Universidad de Granada- takes part in the SINANO network of excellence (Silicon-based Nanodevices).
SINANO brings together a total of 44 universities, research centres, and companies from 16 countries in order to contribute in the development of silicon devices. SINANO network also joins the best European research groups on semi-conductors to draw up a research programme which satisfies the needs of NanoCMOS (Complementary Metal Oxide Semi-conductor). The NanoCMOS project focuses on R+D activities to develop the manufacturing process of the most advanced chips.
”Microelectronics tend more and more to make smaller products. A device with very small dimensions offers more and better performance because it works faster and undertake millions of different functions in only one chip”, according to Francisco Gámiz Pérez, professor of the Department of Electronics and Computing Technology of the UGR.
Integrated circuits or chips consist of several electronic components which have been made over the silicon substrate itself, in such a way that semi-conductor properties of this material are also used. However, according to experts, this conventional support presents serious physical limitations when the dimensions of the device approach nanometres. As a result, the semi-conductor industry has been forced to search for and implement new techniques to manufacture integrated circuits, using new materials and new designs.
Silicon over insulating material
It is worth highlighting all the activities related to the technology of silicon the over Insulating material (SOI), “the future technology” as it is known in that sector. A thin silicon layer holds transistors of chips over an insulating material, allowing designs of very few nanometres in size. In the words of professor Gámiz, “ the insulation allows these transistors to be placed very close together, avoiding interactions or noise among them”. In this way, electronic circuits can become smaller (because they save space) and more effective, enabling the development of more competitive products (cheaper and better performance), such as mobile phones integrated in only one chip.
SINANO network includes partners with expertise required in developing these advanced devices, from basic-materials science through design and manufacture to characterisation, device modelling, and simulation work, which are needed to pass from 1 node (minimum size of a device) of 45 nanometres to another of 32 nanometres.
“The current commercial size is 90 nanometres, although there are already applications with a node of 65 nanometres,” states Francisco Gámiz.
The research of Granada within this network is related to simulation and device modelling undertaken by the technologic groups which comprise the network (leading companies and European Technological centres: STMicroelectronics, Freescale, Philips, Infineon, IMEC, INPG, etc.).
From technical specifications and future applications of devices, researchers of Granada build mathematical patterns which simulate the operation of devices. Therefore, it is possible to understand the performance and thus the improvement of their design. In short, “we wish to achieve a final product with high performance and lower manufacturing costs”.
Reference
Francisco J. Gámiz Pérez. Departamento de Electrónica y Tecnología de Computadores (Department of Electronics and Computing Technology)
Tel. +34 958 246 145 / +34 958 248 532. Email. fgamiz@ugr.es
